The TPS3123J18DBVT is an ultralow voltage processor Supervisory Circuit with active-low push-pull output. The supervisory circuit provides circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power-on, /RESET is asserted when the supply voltage (VDD) becomes higher than 0.75V. Thereafter, the supply voltage supervisor monitors VDD and keeps /RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td=180ms, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. It has a fixed-sense threshold voltage (VIT) set by a high precision internal voltage divider.
- Manual reset input
- Watchdog timer retriggers the /RESET output at VDD >= VIT
- power-ON reset generator with fixed delay time of 180ms
- 14μA Typical supply current
- Green product and no Sb/Br
计算机和计算机周边, 便携式器材, 无线, 工业, 传感与仪器
