The TL16C554IFN is an Asynchronous Communications Element features that each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered. The quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal functions allow signalling of direct memory access (DMA) transfers.
False start bit detection
Complete status reporting capabilities
Line break detection and generation
Loopback controls for communications link fault isolation
Break, parity, overrun and framing-error simulation
Fully prioritized interrupt system controls
3-state Outputs provide TTL drive capabilities for bidirectional data bus and control bus
MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
Consists of four improved TL16C550 ACEs plus steering logic
Adds or deletes standard asynchronous communication bits to or from the serial-data stream
Up to 16-MHz clock rate for up to 1-Mbaud operation
(EN)
