The SN74LS92N is a monolithic Divide-by-Twelve Counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a 3-stage binary counter for which the count cycle length is divide-by-five for the divide-by-six for the LS92. This counter has a gated zero reset suitable for use in BCD nines complement applications. To use their maximum count length of this counter, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table.
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