The SN65LVDS93ADGG is a LVDS SerDes (serializer/deserializer) FlatLink? Transmitter contains four 7-bit parallel load serial-out shift registers, a 7 x clock synthesizer and five low-voltage differential signalling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928). When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
- LVDS display SerDes interfaces directly to LCD display panels with integrated LVDS
- Suited for display resolutions ranging from HVGA up to HD with low EMI
- Consumes less than 1mW when disabled
- Selectable rising or falling clock edge triggered inputs
- Supports spread spectrum clocking (SSC)
- Compatible with all OMAP?2x, OMAP3x and DaVinci? application processors
- 1.8 to 3.3V Tolerant data input to connect directly to low-power, low-voltage and graphic processors
- 10 to 135MHz Pixel clock frequency range
- 5kV HBM ESD
- Green product and no Sb/Br
计算机和计算机周边, 成像, 视频和目视, 通信与网络
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