The SN65LVDS32PW is a quad differential Line Receiver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speed and allow operation with a 3.3V supply rail. Any of the differential receivers provides a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. The intended application of this device and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables.
Low-voltage TTL (LVTTL) logic output levels
Pin-compatible with AM26LS32, MC3486 and μA9637
Open-circuit failsafe
Cold sparing for space and high-reliability applications requiring redundancy
Bus-terminal ESD protection exceeds 8kV
±100mV Maximum differential input thresholds
2.1ns Typical propagation delay time
Power dissipation 60mW typical per receiver at maximum data rate
(EN)
