The LMK00725PW is a high-performance clock Fan-out Buffer can distributes up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability.
- Two differential input pairs
- Synchronous clock enable
- 43fs RMS typical at 312.5MHz additive jitter
- 35ps Maximum output skew
- 100ps Maximum part-to-part skew
- Green product and no Sb/Br
无线, 医用, 通信与网络, 测试与测量, 便携式器材
(EN)
