The DS92LV1212AMSA/NOPB is a 10-bit bus LVDS Random Lock Deserializer with embedded clock recovery. It is designed to be used with the DS92LV1021 bus LVDS serializer. The DS92LV1212A receives a bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock. The reduced cable, PCB trace count and connector size saves cost and makes PCB layout easier. Clock-to-data and data-to-data skews are eliminated since one input receives both clock and data bits serially. The power-down pin is used to save power by reducing the supply current when the device is not in use. The deserializer will establish lock to a synchronization pattern within specified lock times but it can also lock to a data stream without SYNC patterns.
Clock recovery without SYNC patterns-random lock
Guaranteed transition every data transfer cycle
Single differential pair eliminates multi-channel skew
10-bit Parallel interface for 1 bytes data plus 2 control bits or UTOPIA I interface
Synchronization mode and lock indicator
Flow-through pin-out for easy PCB layout
High impedance on receiver inputs when power is off
Programmable edge trigger on clock
Footprint compatible with DS92LV1210
<300mW (typical) at 40MHz Power consumption
400Mbps Serial bus LVDS bandwidth (at 40MHz clock)
(EN)
