The DS90CR286MTD/NOPB is a rising edge data strobe LVDS Receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66MHz, 28 bits of TTL data are transmitted at a rate of 462Mbps per LVDS data channel. Using a 66MHz clock, the data throughput is 1.848Gbps (231Mbps). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the channel link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed.
Narrow bus reduces cable size
PLL requires no external components
Chipset (TX + RX) power consumption of <250mW (typical)
