The CDCP1803RGET is a Clock Driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y(2:0) and Y(2:0) with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50R transmission lines. It has three control terminals, S0, S1 and S2, to select different output mode settings; see for details. It is characterized for operation from -40 to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
- Distributes one differential clock input to three LVPECL differential clock outputs
- Programmable output divider for two LVPECL outputs
- Differential input stage for wide common-mode range
- Provides VBB bias voltage output for single-ended input signals
- 15ps Typical low-output skew
- Green product and no Sb/Br
时钟与计时
