The CDCLVD110ARHBT is a programmable low-voltage Clock Driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0-Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50R transmission lines. When the control enable is high (EN=1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10-bit loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled. The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.
- <30ps Typical low-output skew for clock-distribution
- Distributes one differential clock input to ten LVDS differential clock outputs
- 2.5V at ±5% VCC range
- Typical signalling rate capability of up to 1.1GHz
- Full rail-to-rail common-mode input range
- ±100mV Receiver input threshold
- Green product and no Sb/Br
工业, 消费电子产品, 通信与网络
(EN)
