The ADS5295EVM is an evaluation module for ADS5295 ADC. Low power consumption and integration of multiple channels in a compact package make the ADS5295 attractive for very high channel count data acquisition systems. Serial LVDS outputs reduce the number of interface lines and enable high system integration. The ADC digital data can be output over one or two wires of LVDS pins per channel. At high sample rates, the two wire interface helps to keep the serial data rate low, allowing low cost FPGA based receivers to be used. The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.
Low frequency noise suppression mode
Serial LVDS ADC data outputs
Channel averaging mode
SNR of 70.6dBFS
SFDR of 85dBc at 10MHz and 100MSPS
Programmable mapping between ADC input channels and LVDS output pins
Digital processing block
Variety of LVDS test patterns to verify data capture by FPGA or receiver
Programmable FIR decimation filter and oversampling to minimize harmonic interference
Programmable IIR high pass filter to minimize DC offset
(EN)
