The STWD100YNPWY3F is a Watchdog Timer Circuit with chip enable input and active-low open-drain output. The watchdog timer circuit is self-contained device which prevent system failures that are caused by certain types of hardware errors (such as, non-responding peripherals and bus contention) or software errors (such as bad code jump and code stuck in loop). The STWD100 watchdog timer has an input, WDI and an output, WDO. The input is used to clear the internal watchdog timer periodically within the specified timeout period, twd. While the system is operating correctly, it periodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is not reset, a system alert is generated and the watchdog output, WDO, is asserted. The STWD100 circuit also has an enable pin, EN, which can enable or disable the watchdog functionality. The EN pin is connected to the internal pull-down resistor. The device is enabled if the EN pin is left floating.
- 13μA Typical current consumption
- 2000V HBM and 1000V RCDM ESD performance
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