The S25FL256SAGBHI200 is a 256MB MirrorBit? Flash Non-Volatile Memory CMOS 3V core with versatile I/O serial peripheral interface with multi-I/O. This family of devices connects to a host system via a serial peripheral interface (SPI). In addition, the FL-S family adds support for double Data rate read commands for SIO, DIO and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.
- SPI Clock polarity and phase modes 0 and 3
- Multi I/O Command set and footprint compatible with S25FL-P SPI family
- Common Flash Interface (CFI) data for configuration information
- Quad-input page programming (QPP) for slow clock systems
- Cycling endurance - 100000 program-erase cycles on any sector typical
- Data retention - 20 years data retention typical
- One time program (OTP) array of 1024 bytes
- Status register bits to control protection against program/erase of a contiguous range of sectors
- Individual sector protection controlled by boot code or password
- Spansion? 65nm MirrorBit technology with Eclipse? Architecture
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