The PCA9515AD,112 is a CMOS Integrated Circuit intended for application in I2C-bus and SMBus systems. While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400pF. The I2C-bus capacitance limit of 400pF restricts the number of devices and bus length. Using the PCA9515A enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5V and the other at 3.3V or a 400 and 100kHz bus, where the 100kHz bus is isolated when 400kHz operation of the other is required. The output pull-down of each internal buffer is set for approximately 0.5V, while the input threshold of each internal buffer is set about 0.07V lower, when the output is internally driven LOW. This prevents a lock-up condition from occurring.
- 2-channel Bidirectional buffer
- I2C-bus and SMBus compatible
- Active high repeater enable input
- Open-drain input/outputs
- Lock-up free operation
- Supports arbitration and clock stretching across the repeater
- Accommodates standard-mode and fast-mode I2C-bus devices and multiple masters
- Powered-OFF high-impedance I2C-bus pins
- Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
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