The PCA9511AD,112 is a hot swappable I2C Bus and SMBus Buffer allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, it provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. It incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption
Built-in ?V/?t rise time accelerators on all SDA and SCL lines
Active HIGH ENABLE input
Active HIGH READY open-drain output
1V precharge on all SDA and SCL lines
Supporting clock stretching and multiple master arbitration/synchronization
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
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