The MPC860 PowerQUICC? versatile one-chip Integrated Microprocessor and Peripheral Combination designed for a variety of controller applications. The PowerQUICC? unit is referred to as the MPC860 in this hardware specification. The MPC860 implements Power Architecture? technology and contains a superset of Freescale's MC68360 quad integrated communications controller (QUICC), referred to here as the QUICC, RISC communications processor module (CPM). The CPU on the MPC860 is a 32-bit core built on power architecture technology that incorporates memory management units (MMUs) and instruction and data caches. The CPM from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated.
- Up to 32-bit data bus (dynamic bus sizing for 8, 16 and 32 bits)
- 32 Address lines
- Operates at up to 80MHz
- Memory controller (eight banks) - Each bank can be a chip select or RAS to support a DRAM bank
- General-purpose timers - Four 16-bit timers or two 32-bit timers
- System integration unit (SIU) - Bus monitor, software watchdog and periodic interrupt timer (PIT)
- Interrupts - Seven external interrupt request (IRQ) lines and 12 port pins with interrupt capability
- 10/100Mbps Ethernet support
- ATM support compliant with ATM forum UNI 4.0 specification
- Communications processor module (CPM) - RISC communications processor (CP)
- Four baud-rate generators (BRGs) - Independent (can be tied to any SCC or SMC)
- Four serial communications controllers (SCCs) - Synchronous UART and AppleTalk
- Two SMCs (serial management channels) - UART and general circuit interface (GCI) controller
- Time-slot assigner (TSA)
- Parallel interface port (PIP)
- PCMCIA interface - Supports eight memory or I/O windows
- Low power support
- Debug interface
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