The LPC11E68JBD100E is a 32-bit Microcontroller based on ARM Cortex-M0+ core with RISC architecture operates at a maximum frequency of 50MHz. The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline and fast single-cycle I/O access. The device incorporates 256kB internal flash, 36kB internal RAM, 4kB EEPROM, both standard and configurable timers/PWMs for advanced timing requirements, 12-channel 12-bit A/D converter with sample rates of up to 2Msps and 80 general-purpose I/O pins. This device also features peripherals like five USARTs and two inter-integrated circuit (I2C).
- ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC)
- AHB multilayer matrix
- System tick timer
- Serial wire debug (SWD) and JTAG boundary scan modes supported
- Micro trace buffer (MTB) supported
- Flash in-application programming (IAP) and In-system programming (ISP)
- 32-bit Integer division routines
- Simple DMA engine with 16 channels and programmable input triggers
- Pin interrupt and pattern match engine using eight selectable GPIO pins
- Two GPIO group interrupt generators
- CRC Engine
- Configurable PWM/timer subsystem
- Windowed watchdog timer (WWDT)
- Real-time clock (RTC) in the always-on power domain
- Two SSP controllers with DMA support
- 12MHz Internal RC oscillator trimmed to 1 % accuracy
- 32kHz On-chip oscillator for RTC
- Crystal oscillator with an operating range of 1MHz to 25MHz
- Programmable watchdog oscillator with a frequency range of 9.4kHz to 2.3MHz
- PLL allows CPU operation up to the maximum CPU rate
计量, 通信与网络, 消费电子产品, 车用, 计算机和计算机周边, 医用
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