The MT48LC16M16A2P-7E is a 256MB high-speed CMOS SDRAM with 133MHz clock frequency. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). 256MB SDRAM device (4 Meg x 16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Each of the x4s 67108864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an active command, followed by a read or write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A(12:0) select the row).
Fully synchronous, all signals registered on positive edge of system clock
Internal, pipelined operation, column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Auto precharge, includes concurrent auto precharge and auto refresh modes
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