The JS28F512P33EFA is a 512MB NOR Flash Memory provides high performance on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power-up or return from reset, the device defaults to asynchronous page-mode read. Configuring the RCR (read configuration register) enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast buffer program and erase operations. The device features a 512-word buffer to enable optimum programming performance, which can improve system programming throughput time significantly to 1.46Mbyte/s. Designed for low-voltage systems, P33-65nm device supports read operations with VCC at 3V and erase and program operations with VPP at 3/9V.
- High performance - 95ns initial access time
- Symmetrically-blocked architecture
- Blank check to verify an erased block
- Continuous synchronous read current - 21mA typical/24mA maximum at 52MHz
- Enhanced security
- Absolute write protection - VPP = VSS
- Power-transition erase/program lockout
- Individual zero-latency block locking
- Individual block lock-down capability
- Numonyx? Flash data integrator optimized
- Basic command set and extended function Interface (EFI) command set compatible
- Common flash interface capable
- Minimum 100000 erase cycles
计算机和计算机周边, 工业, 通信与网络, 消费电子产品
