The LAN91C111-NU is a 10/100 non-PCI Ethernet Controller designed to facilitate the implementation of a third generation of fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal analogue/digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100Mbps. The design will also minimize data throughput constraints utilizing a bus host interface. The total internal memory FIFO buffer size is 8kB, which is the total chip storage for transmit and receive operations. The LAN91C111 is software compatible with the LAN9000 family of products.
Single chip Ethernet controller
Dual speed - 10/100Mbps
Fully supports full duplex switched Ethernet
Supports burst data transfer
8kB Internal memory for receive and transmit FIFO buffers
Enhanced power management
Optional configuration via serial EEPROM interface
Supports 8, 16 and 32 bit CPU accesses
Internal 32-bit wide data path (into packet buffer memory)
Built-in transparent arbitration for slave sequential access architecture
Flat MMU architecture with symmetric transmit and receive structures and queues
3.3V Operation with 5V tolerant I/O buffers
Single 25MHz reference clock for both PHY and MAC
External 25MHz output pin for an external PHY supporting PHY's physical media
(EN)
