The DSPIC30F6014A-30I/PT is a 16-bit high-performance Digital Signal Controller feature high-performance modified RISC CPU. The program counter (PC) is 23-bits wide with the least significant bit (LSb) always clear and the most significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls. The data space is 64Kbytes (32K words) and is split into two blocks, referred to as X and Y data memory.
Modified Harvard architecture
C compiler optimized instruction set architecture
Flexible addressing modes
83 Base instructions
Eight user-selectable priority levels
Five external interrupt sources
Four processor traps
Dual data fetch
Modulo and bit-reversed modes
Two 40-bit wide accumulators with optional saturation logic
16-bit Capture input functions
16-bit Compare/PWM output functions
Two addressable UART modules with FIFO buffers
Two CAN bus modules compliant with CAN 2.0B standard
