The DSPIC30F6010A-30I/PT is a 16-bit high-performance Digital Signal Controller features CPU core has a 24-bit instruction word. The Program Counter (PC) is 23-bit wide with the least significant bit (LSb) always clear and the most significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
Modified Harvard architecture
C-compiler optimized instruction set architecture
84 base instructions with flexible addressing modes
24-bit wide instructions, 16-bit wide data path
16 x 16-bit working register array modes
DSP engine - Modulo and bit-reversed addressing modes
Peripheral features - 3-wire SPI? modules
Motor control PWM module - Complementary or independent output modes
Quadrature encoder interface module - 16-bit up/down position counter
10-bit 1MSPS analogue-to-digital converter (A/D)
Enhanced flash program memory - 10,000 erase/write cycle (minimum)
Data EEPROM memory - 100000 erase/write cycle (minimum)
