The DSPIC30F4013-30I/PT is a 16-bit high-performance Digital Signal Controller with seamless migration options from this device to dsPIC33F and PIC24 devices. The CPU core has a 24-bit instruction word. The Program Counter (PC) is 23-bit wide with the least significant bit (LSb) always clear and the most significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
Modified Harvard architecture
C-compiler optimized instruction set architecture
84 base instructions with flexible addressing modes
16-bit Wide data path
16 x 16-bit working register array modes
DSP engine - Modulo and bit-reversed addressing modes