The DS1100LU-50+ is a 3.3V 5-tap economy timing element (delay line) in 8 pin μMAX package. It is characterized for operation over the range 3V to 3.6V. The DS1100LU-50+ delay line has five equally spaced taps. It is offered in surface-mount packages to save PCB area. This 5-tap silicon delay line reproduces the input-logic state at the output after a fixed delay of 50ns and it has 10ns delay time per tap. It is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to 10 74LS loads.
(EN)
