The S912ZVMC12F1MKH is a MagniV mixed signal S12ZVM-family 16-bit Microcontroller using the NVM + UHV technology that offers the capability to integrate 40V analog components. This family reuses many features from the existing S12/S12X portfolio. The particular differentiating features of this family are the enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the integration of "high-voltage" analog modules, including the voltage regulator, Gate Drive Unit and either Local Interconnect Network physical layer or CAN Physical layer. The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family allows the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings.
- Harvard architecture - parallel data and code access
- 3-Stage pipeline
- 32-bit Wide instruction and data bus
- 32-bit ALU
- 24-bit Addressing (16MB linear address space)
- Phase locked loop (IPLL) frequency multiplier with internal filter
- 1MHz Internal RC oscillator with +/-1.3% accuracy
- 4-20MHz Amplitude controlled pierce oscillator
- Internal COP (watchdog) module
- 6-channel, 15-bit pulse width modulator with fault protection (PMF)
- Low side and high side FET pre-drivers for each phase
- 2 Parallel ADC with 12-bit resolution
- Programmable trigger unit (PTU) for synchronization of PMF and ADC
- Serial peripheral interface (SPI) module
- SCI module with interface to internal LIN physical layer transceiver
- Additional SCI (not connected to LIN physical layer)
- 4-channel Timer module (TIM0) with input capture/output compare
- MSCAN (1Mbps, CAN 2.0 A, B software compatible) module
- On-chip voltage regulator (VREG)
- 2 Current sense circuits for overcurrent detection or torque measurement
电机驱动与控制, 车用
