The DM9000BEP is a fully integrated low pin count single chip Fast Ethernet Controller with a general processor interface, a 10/100M PHY and 4K DWORD SRAM. It is designed with low power and high performance process interface that support 3.3V with 5V IO tolerance. The DM9000B supports 8-bit and 16-bit data interfaces to internal memory accesses for various processors. The PHY of the DM9000B can interface to the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX. It is fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000B to take the maximum advantage of its abilities. The DM9000B also supports IEEE 802.3x full-duplex flow control.
Supports processor interface, byte/word of I/O command to internal memory data operation
Integrated 10/100M transceiver with HP auto-MDIX
Supports back pressure mode for half-duplex
IEEE802.3x flow control for full-duplex mode
Supports wakeup frame, link status change and magic packet events for remote wake up
Support 100M fibre interface
Integrated 16kB SRAM
Build in 3.3 to 1.8V regulator
Supports early transmit
Supports IP/TCP/UDP checksum generation and checking
Supports automatically load vendor ID and product ID from EEPROM
