The ADSP-21062LCSZ-160 is a SHARC? Signal Processing Microcomputer offers high levels of DSP performance. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system on a chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25ns instruction cycle time and operates at 40MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. It represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated on-chip system features including up to 2MB SRAM memory, a host processor interface, DMA controller, serial ports and link port and parallel bus connectivity for glueless DSP multiprocessing.
- Single-cycle loop setup
- Single-cycle instruction execution
- Super Harvard architecture (SHARC)
- IEEE floating-point computation units
- Efficient program sequencing with zero-overhead looping
- IEEE JTAG Standard 1149.1 test access port and on-chip emulation
- Dual data address generators with modulo and bit-reverse addressing
- 120 MFLOPS peak, 80 MFLOPS sustained performance
- 4 Independent buses for dual data fetch, instruction fetch and nonintrusive I/O
- 40MHz Instruction rate
成像, 视频和目视, 通信与网络, 信号处理
