The AD9548/PCBZ is an evaluation board for quad/octal input network clock generator/synchronizer AD9548. The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.
- It supports stratum-2 stability in holdover mode
- It supports reference switchover with phase build-out
- It supports hitless reference switchover
- It provides Auto/manual holdover and reference switchover
- It provides 4 pairs of reference input pins with each pair configurable
- It has input reference frequencies from 1Hz to 750MHz
- It has reference validation and frequency monitoring (1ppm)
- It provides programmable input reference switchover priority
- It has 30 bit programmable input reference divider
- It has programmable digital loop filter
通信与网络, 时钟与计时, 无线
(EN)
