The AD9528BCPZ is a 14-output LVDS/HSTL Clock Generator for use with LTE and multicarrier GSM base stations. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The integrated SYSREF generator outputs single shot, N-shot or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analogue fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs.
Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy
Dedicated 8-bit dividers on each output
20ps Typical output to output skew
Duty cycle correction for odd divider settings
Digital frequency lock detect
SPI and I2C-compatible serial control port
Dual PLL architecture
Provides reference input clock clean-up with external VCXO
