The AD9523-1BCPZ is a 14-output low jitter Clock Generator with LVPECL/LVDS/HSTL/29 LVCMOS outputs. It provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 to 3.1GHz. The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter clean-up to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. The input receivers, oscillator and zero delay receivers provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1MHz to 1GHz and one dedicated buffered output from the input PLL (PLL1).
- Low bandwidth for reference input clock clean-up with external VCXO
- Automatic and manual reference switchover modes
- Digital lock detect
- Non-volatile EEPROM stores configuration settings
- SPI- and I2C-compatible serial control port
- Dual PLL architecture
- Duty cycle correction for odd divider settings
- Automatic synchronization of all outputs on power-up
- Dual VCO dividers
- Zero delay operation
无线, 传感与仪器, 医用
