The AD9510BCPZ is a 8-output Clock Distribution IC provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device. By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6GHz can be synchronized to the input reference. Four outputs are low voltage positive emitter-coupled logic (LVPECL) at 1.2GHz and four are selectable as either LVDS (800MHz) or CMOS (250MHz) levels. Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment.
Low phase noise phase-locked loop core
Reference input frequencies to 250MHz
Programmable dual modulus pre-scalar
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Phase select for output-to-output coarse delay adjust
Complementary metal oxide conductor (CMOS) clock outputs
(EN)
