The AD9250-250EBZ is an evaluation board to evaluate AD9250BCPZ-250 ADC. The AD9250BCPZ-250 is a dual, 14bit ADC with sampling speeds of up to 250MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. Flexible power down options allow significant power savings, when desired.
- 1.8V supply voltage
- User configurable, built in self test (BIST) capability
- Energy saving power down modes
- Serial port control
- 95dB channel isolation/crosstalk
- ADC clock duty cycle stabilizer (DCS)
- Integer 1 to 8 input clock divider
- IF sampling frequencies of up to 400MHz
- Total power consumption of 711mW at 250MSPS
- Support for an optional RF clock input to ease system board design
通信与网络, 无线, 测试与测量
