The AD9235BCPZ-65 is a monolithic Analog-to-digital Converter (ADC) uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including 1-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling 1-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADC. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats.
Offset binary or twos complement data format
Clock duty cycle stabilizer
High performance sample-and-hold amplifier and voltage reference
