The AD7787BRMZ is a 2-channel 24-bit Low Power Sigma-Delta (Σ-Δ) ADC for low frequency measurement applications. It contains a low noise 24-bit Σ-Δ ADC with one differential input and one single ended input that can be buffered or unbuffered. The complete analogue front end device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5Hz to 120Hz, with the RMS noise equal to 1.1μV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4 or 8, which leads to a reduction in the current consumption. The update rate, cut-off frequency and settling time scales with the clock frequency. The part operates with a power supply from 2.5 to 5.25 V. When operating from a 3V supply, the power dissipation for the part is 225μW maximum.
- 1.1μV RMS noise at 9.5Hz update rate
- 19.5-bit p-p resolution (22-bit effective resolution)
- 3.5ppm Typical integral nonlinearity
- Simultaneous 50 and 60Hz rejection
- Internal clock oscillator
- Rail-to-rail input buffer
- VDD monitor channel
电源管理, 便携式器材, 传感与仪器, 测试与测量
(EN)
